Hardware Acceleration of the Embedded Zerotree Wavelet Algorithm

The goal of this project was to gain experience in designing and implementing a microelectronic system to acclerate the execution of a time-consuming software algorithm, the Embedded Zerotree Wavelet (EZW), which is used in multimedia applications. The algorithm was implemented using MATLAB to be certain it was fully understood and to serve as a validation reference. Then, the algorithm was mapped into a hardware description language, VHDL, and its resulting implementation verified with the golden reference. The hardware description was then targeted to a field-programmable gate array (FPGA). Significant acceleration was achieved since the hardware implementation in a FPGA (Xilinx Virtex-1000E using a 8.315 MHz clock) ran 10,000 times faster than the MATLAB implementation on a SUN-220 workstation. Additional speedup exploiting the parallel capabilities of the FPGA was not achieved since the EZW algorithm utilizes only sequential operations

HARDWARE ACCELERATION OF THE EMBEDDED ZEROTREE WAVELET ALGORITHM

I am submitting herewith a thesis written by Suresh S. Polisetty entitled "Hardware Acceleration of the Embedded Zerotree Wavelet Algorithm. " I have examined the final electronic copy of this thesis for form and content and recommend that it be accepted i